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Hynix Semiconductor Inc. v. Rambus Inc.

February 23, 2006

HYNIX SEMICONDUCTOR INC., HYNIX SEMICONDUCTOR AMERICA INC., HYNIX SEMICONDUCTOR U.K. LTD., AND HYNIX SEMICONDUCTOR DEUTSCHLAND GMBH, PLAINTIFFS,
v.
RAMBUS INC., DEFENDANT.



The opinion of the court was delivered by: Ronald M. Whyte United States District Judge

Date: 2/23/06 DOH

Chambers of Judge Whyte

ORDER DENYING RAMBUS'S MOTION FOR SUMMARY JUDGMENT OF INFRINGEMENT RELATING TO "DELAY LOCKED LOOP" [Re Docket No. 1020]

Rambus seeks summary judgment that the Double Data Rate Synchronous Dynamic Random Access Memory ("DDR SDRAM") devices of Hynix*fn1 infringe claim 33 of U.S. Patent No. 6,034,918 ("the '918 patent"), claim 38 of U.S. Patent No. 6,324,120 ("the '120 patent"), claim 40 of U.S. Patent No. 6,426,916 ("the '916 patent"), and claim 34 of U.S. Patent No. 5,915,105 ("the '105 patent") (collectively "claims-at-issue"). The court has read the moving and responding papers and considered the arguments of counsel. For the reasons set forth below, the court DENIES summary adjudication that Hynix's accused devices contain elements covered by the "delay locked loop" limitation. Rambus's assertion that the accused devices meet the agreed-upon construction of "delay locked loop" is subject to a material issue of fact and, therefore, summary judgment of infringement on claim 33 of U.S. Patent No. 6,034,918, claim 38 of U.S. Patent No. 6,324,120, claim 40 of U.S. Patent No. 6,426,916, and claim 34 of U.S. Patent No. 5,915,105 is DENIED.

I. BACKGROUND

On January 19, 2005, the court issued its Clarified and Corrected Order on Rambus's Motion for Summary Judgment of Infringement, ruling that Hynix's accused devices infringed several of Rambus's patents, including the claims-at-issue. Hynix failed to argue in response to Rambus's motion that its accused products did not meet the "delay locked loop" limitation. On January 24, 2005, Hynix moved for relief from the court's ruling. On February 11, 2005, prior to the court ruling on its motion for relief, Hynix moved for summary judgment that Rambus's patents are invalid for failure to meet the written description requirement with respect to the "delay locked loop" limitation. The court has denied Hynix's motion. See Order Denying Hynix's Motion for Summ. J. of Invalidity of Patent Claims Including "Delay Locked Loop."

The court granted Hynix's motion for relief on March 4, 2005 but permitted Rambus to move for summary judgment on claims including the "delay locked loop" limitation. Accordingly, on April 1, 2005, Rambus filed the present motion seeking summary judgment of infringement of claims including the "delay locked loop" limitation.

Rambus asserts that Hynix's DDR SDRAM devices infringe the '918, '120, '916 and '105 patents. The patents-at-issue in this motion descend from an original patent application filed on April 18, 1990 and contain essentially identical written descriptions. The issue raised in this motion is whether Hynix's accused DDR SDRAM products contain elements covered by the limitation "delay locked loop."

The parties have stipulated to the construction of the limitation here at issue. The parties' agreed construction of "delay locked loop" is: circuitry on the device, including a variable delay line, that uses feedback to adjust the amount of delay of the variable delay line and to generate a signal having a controlled timing relationship relative to another signal.

Joint Claim Construction and Prop. at 3. Rambus's motion relies heavily upon apparent conflict between Hynix's invalidity contentions regarding the lack of written description for a "delay locked loop" in the patent specification and its non-infringement position with regard to the same limitation.

II. ANALYSIS

Each of the claims-at-issue are dependent claims reciting the term "delay locked loop" as an additional limitation to the corresponding independent claims in the '918 patent (claim 18), '120 patent (claim 26), '916 patent (claim 26), and '105 patent (claim 36). Claim 38 of the '120 patent is exemplary of the use of "delay locked loop" in the asserted claims:

38. The memory device of claim 26 further including delay locked loop circuitry coupled to the clock receiver circuitry to generate an internal clock signal, wherein the plurality of output drivers ...


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