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Hynix Semiconductor Inc. v. Rambus Inc.

February 28, 2006

HYNIX SEMICONDUCTOR INC., HYNIX SEMICONDUCTOR AMERICA INC., HYNIX SEMICONDUCTOR U.K. LTD., AND HYNIX SEMICONDUCTOR DEUTSCHLAND GMBH, PLAINTIFFS,
v.
RAMBUS INC., DEFENDANT.



The opinion of the court was delivered by: Ronald M. Whyte United States District Judge

ORDER DENYING HYNIX'S MOTION FOR SUMMARY JUDGMENT OF INVALIDITY OF U.S. PATENT Nos. 6,378,020 AND 5,915,105 UNDER 35 U.S.C. §§ 102 AND/OR 103 [Re Docket No. 763]

Hynix seeks summary judgment of invalidity based on two prior art references that it contends render claims 32 and 36 of U.S. Patent No. 6,378,020 ("the '020 patent"), and claim 34 of U.S. Patent No. 5,915,105 ("the '105 patent") obvious or anticipated under 35 U.S.C. §§ 102 and 103. Rambus opposes the motion. The court has read the moving and responding papers and considered the arguments of counsel. For the reasons set forth below, the court DENIES Hynix's motion for summary judgment.

I. BACKGROUND

A. U.S. Patent No. 4,330,852 ("Redwine")

The Redwine patent, filed on November 23, 1979 and issued on May 18, 1982, discloses a "Semiconductor Read/Write Memory Array Having Serial Access."

B. U.S. Patent No. 4,922,141 ("Lofgren")

The Lofgren patent, filed on June 3, 1988 and issued on May 1, 1990, discloses a "Phase-Locked Loop Delay Line."

The Patent Examiner considered the Redwine patent duringprosecution of the '020 patent, but did not consider Redwine during prosecution of the '105 patent. In addition, the Patent Examiner did not consider Lofgren during prosecution of either the '020 or '105 patents.

C. Invalidity and Obviousness Contentions

Hynix contends that asserted claim 32 of the '020 patent (and claims 30 and 31 upon which claim 32 relies) is anticipated by the Redwine patent and therefore rendered invalid under 35 U.S.C. § 102. In addition, Hynix argues that asserted claim 36 of the '020 patent (and claim 35 upon which claim 36 relies) is obvious in light of the Redwine patent in combination with the Lofgren patent. See 35 U.S.C. § 103. Finally, Hynix asserts that claim 34 of the '105 patent is invalid as obvious in light of Redwine in combination with Lofgren.*fn1 See id.

II. ANALYSIS

A. Asserted Claim 32 of the '020 Patent

A person is not entitled to a patent if the invention was patented or described in a printed publication more than one year prior to the date of the application, under Section 102(b), or prior to the date of conception, under Section 102(a). See 35 U.S.C. § 102. "To anticipate a claim, a prior art reference must disclose every limitation of the claimed invention, either explicitly or inherently." Minnesota Mining & Mfg. Co. v. Johnson & Johnson Orthopaedics, Inc., 976 F.2d 1559, 1565 (Fed. Cir. 1992); Atlas Powder Co. v. Ireco Inc., 190 F.3d 1342 (Fed. Cir. 1999); Glaxo Inc. v. Novopharm Ltd., 52 F.3d 1043, 1047 (Fed. Cir. 1995). The question of whether a claim limitation is inherent in a prior art reference is a factual issue on which evidence may be introduced. See Diversitech Corp. v. Century Steps, Inc., 850 F.2d 675, 677 (Fed. Cir. 1988); Continental Can Co. USA v. Monsanto Co., 948 F.2d 1264, 1268 (Fed. Cir. 1991); In re Graves, 69 F.3d 1147, 1151 (Fed. Cir. 1995); In re Schrieber, 128 F.3d 1473, 1477 (Fed. Cir. 1997). Because anticipation is generally an issue of fact, "[t]he burden of proving invalidity on summary judgment is high[,]" i.e., clear and convincing. Schumer v. Laboratory Computer Systems, Inc., 308 F.3d 1304, 1316 (Fed. Cir. 2002).

In defining the meaning of key terms in a claim, a party may reference the specification, the prosecution history, prior art, and other claims. See Monsanto, 948 F.2d at 1268 ("entirely proper" to use specification to determine what inventor meant by terms and phrases in claims). However, it is the claims of the patent that must be anticipated, since the claims define the invention. See Constant v. Advanced Micro-Devices, Inc., 848 F.2d 1560, 1571 (Fed. Cir. 1988).

1. Independent Claim 30 of the '020 Patent (Integrated Circuit Device Limitation)*fn2

Claim 30 recites in part:

An integrated circuit device comprising: input receiver circuitry to sample an operation code synchronously with respect to a first transition of an external clock signal, the operation code specifying a read operation; []

Hynix contends that each limitation of claim 30 is anticipated by the Redwine patent.

Rambus responds, inter alia, that the patent examiner specifically considered the Redwine patent during prosecution, so there is a strong inference that the Redwine patent is not Section 102 prior art. See McGinley v. Franklin Sports, Inc., 262 F.3d 1339, 1353 (Fed. Cir. 2001). The parties agree that the Redwine patent discloses "an integrated circuit device." The parties disagree over whether the Redwine patent discloses the remaining limitations of claim 30.

a. External Clock Signal

"External clock signal" has been construed by this court to mean "a periodic signal from a source external to the device to provide timing information." Claim Construction Order at 30. Hynix argues that the clock generator and control circuitry 30 of the Redwine patent, as represented in block diagram Fig. 1, and the timing diagram of Fig. 2(f)-(h) (a graphic representation of voltage versus time), which references an external clock signal M, meetthis limitation. Mot. at 8; Redwine Chart at 1.

Rambus counters that the Redwine patent does not contain an external clock signal because it lacks the required "periodic signal." More specifically, in Fig. 2(f) of the Redwine patent, M is not periodic. Rambus notes that during both read and write operations there is a time period where M is not signaling. See Murphy Decl. ¶ 44 (citing Fig. 2(f), annotation above Fig. 2(a)).

Hynix argues in reply that Rambus's reliance on Fig. 2(f) of Redwine, without reference to Figs. 1 and 3, is in error. Hynix submits that Redwine Fig. 1 shows that CS*fn3 acts as a gate for the external signal M, while Redwine Fig. 3, in the upper left hand corner, discloses how the external signal M is controlled by CS\ and becomes internal clock signals M1 and M2. Fig. 2(f), in contrast, depicts a period both before a write operation, when the M external clock signal is "gated" by the transistor CS (CS\ stays high), and after CS signals a write operation (when CS\ falls to low). See Taylor Decl. Ex. A at 3, 5-6. Hynix submits that regardless of whether CS is low or high, Redwine Figs. 1 and 3, reviewed in combination with Fig. 2, clearly disclose that the external signal M continues to run periodically and is continuously applied to the input pin. Taylor Decl. ΒΆ 8. Hynix further notes that "[i]t would be unnecessary to have the M external clock signal ...


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