United States District Court, N.D. California
CLAIM CONSTRUCTION ORDER RE: DKT. NO. 163
WILLIAM H. ORRICK UNITED STATES DISTRICT JUDGE
me are six patents from the same patent family, all assigned
to declaratory judgment defendant Tela Innovations, Inc., and
all asserted against plaintiff Intel Corporation. The
patented technology aims to improve the design and
manufacturability of integrated circuits by ameliorating
difficulties associated with the lithographic gap, or the
size difference between ever-shrinking semiconductor features
and the wavelength of light used to fabricate them. The
parties have asked me to construe seven terms from the
asserted claims. My constructions are below.
November 4, 2008 and January 22, 2019, the United States
Patent and Trademark Office (“PTO”) issued United
States Patent Nos. 7, 446, 352 (“the '352
Patent”), 7, 943, 966 (“the '966
Patent”), 7, 948, 012 (“the '012
Patent”), 10, 141, 334 (“the '334
Patent”), 10, 141, 335 (“the '335
Patent”), and 10, 186, 523 (“the '523
Patent”) (collectively, the “patents in
suit”). See Declaration of Frank Liu
(“Liu Decl.”), Exs. 1-6 [Dkt. Nos. 166-2, 166-3,
166-4, 166-5, 166-6, 166-7]. All of the patents in suit are
part of the same patent family, all claim priority to
Provisional Application No. 60/781, 288, filed on March 9,
2006, and all list Tela as the sole assignee.
filed this declaratory judgment action on May 15,
No. 1. Since that time, I have resolved a motion to transfer,
several motions to dismiss and strike, a disputed motion for
a protective order, and several discovery disputes.
See Dkt. Nos. 64, 70, 86, 162. The parties briefed
claim construction starting on June 13, 2019, and each
submitted an electronic technology tutorial in advance of the
claim construction hearing. See Dkt. Nos. 163, 173.
After providing the parties with my tentative opinions, I
heard argument on September 27, 2019. Dkt. Nos. 172, 173.
construction is a matter of law. See Markman v. Westview
Instruments, Inc., 517 U.S. 370, 372 (1996);
Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576,
1582 (Fed. Cir. 1996). “Generally, a claim term is
given its ordinary and customary meaning-the meaning that a
term would have to a person of ordinary skill in the art in
question at the time of the invention.” Howmedica
Osteonics Corp. v. Zimmer, Inc., 822 F.3d 1312, 1320
(Fed. Cir. 2016) (internal quotation marks and citation
omitted). In determining the proper construction of a claim,
a court begins with the intrinsic evidence of record,
consisting of the claim language, the patent specification,
and, if in evidence, the prosecution history. Phillips v.
AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005); see
also Vitronics, 90 F.3d at 1582. “A claim term
used in multiple claims should be construed consistently . .
. .” Inverness Med. Switzerland GmbH v. Princeton
Biomeditech Corp., 309 F.3d 1365, 1371 (Fed. Cir. 2002).
appropriate starting point . . . is always with the language
of the asserted claim itself.” Comark Commc'ns,
Inc. v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir.
1998). “[T]he ordinary and customary meaning of a claim
term is the meaning that the term would have to a person of
ordinary skill in the art in question at the time of the
invention, i.e., as of the effective filing date of the
patent application.” Phillips, 415 F.3d at
1312. “There are only two exceptions to this general
rule: 1) when a patentee sets out a definition and acts as
his own lexicographer, or 2) when the patentee disavows the
full scope of a claim term either in the specification or
during prosecution.” Thorner v. Sony Computer
Entm't Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir.
2012). Such redefinition or disavowal need not be express to
be clear. Trustees of Columbia Univ. in City of New York
v. Symantec Corp., 811 F.3d 1359, 1364 (Fed. Cir. 2016).
read terms in the context of the claim and of the entire
patent, including the specification. Phillips, 415
F.3d at 1313. The specification is “the single best
guide to the meaning of a disputed term.”
Vitronics, 90 F.3d at 1582. “The construction
that stays true to the claim language and most naturally
aligns with the patent's description of the invention
will be, in the end, the correct construction.”
Renishaw PLC v. Marposs Societa' per Azioni, 158
F.3d 1243, 1250 (Fed. Cir. 1998). The court may also consider
the prosecution history of the patent, if in evidence.
Markman, 52 F.3d at 980. The prosecution history may
“inform the meaning of the claim language by
demonstrating how the inventor understood the invention and
whether the inventor limited the invention in the course of
prosecution, making the claim scope narrower than it would
otherwise be.” Phillips, 415 F.3d at 1317
(citing Vitronics, 90 F.3d at 1582-83); see also
Chimie v. PPG Indus., Inc., 402 F.3d 1371, 1384 (Fed.
Cir. 2005) (“The purpose of consulting the prosecution
history in construing a claim is to exclude any
interpretation that was disclaimed during
prosecution.”) (internal quotations omitted).
situations, analysis of the intrinsic evidence alone will
resolve claim construction disputes, Vitronics, 90
F.3d at 1583; however, a court can further consult
“trustworthy extrinsic evidence” to compare its
construction to “widely held understandings in the
pertinent technical field, ” Pitney Bowes, Inc. v.
Hewlett-Packard Co., 182 F.3d 1298, 1309 (Fed. Cir.
1999). Extrinsic evidence “consists of all evidence
external to the patent and prosecution history, including
expert and inventor testimony, dictionaries, and learned
treatises.” Markman, 52 F.3d at 980. All
extrinsic evidence should be evaluated in light of the
intrinsic evidence, Phillips, 415 F.3d at 1319, and
courts should not rely on extrinsic evidence in claim
construction to contradict the meaning of claims discernible
from examination of the claims, the written description, and
the prosecution history, Pitney Bowes, 182 F.3d at
1308 (citing Vitronics, 90 F.3d at 1583).
patents at issue aim to improve the design and
manufacturability of integrated circuits by creating
solutions to manage the lithographic gap. '352 Patent
1:49-51. Integrated circuit chips are the building blocks of
devices like computers, smart phones, and tablets, and
transistors are the building blocks of integrated circuit
chips. Today, a single integrated circuit chip includes
billions of transistors, which form the bottom layer of the
chip, connected to the layers above by metal interconnects.
Transistors are effectively switches that control the flow of
electrical current through a circuit.
are made up of a substrate, a source region, a drain region,
and a gate. A semiconductor material forms the substrate. The
source and drain regions have the same charge, either
positive or negative, which is created by introducing
impurities during the fabrication process. The transistor
gate can be made of metal or polysilicon. Voltage applied to
the transistor gate determines whether a channel forms
underneath the gate, allowing charge to flow between the
source and drain regions. When the opposite charge is applied
to the gate, a current begins to flow through the substrate
between the source and drain regions (i.e., the transistor is
of integrated circuits occurs one layer at a time, beginning
with the bottom transistor layer, known as the front end. To
fabricate transistors, different materials are added,
altered, and removed until the desired features are present.
The Asserted Patents are primarily directed to one tool used
during fabrication, called photolithography, or lithography.
Lithography is used to create a specific pattern of gates on
the substrate. Once the gate material has been deposited onto
the substrate, a material called photoresist, which is
sensitive to light, is placed on top. A light is shone through a patterned
mask, altering the chemical nature of the photoresist that it
reaches and creating the desired pattern. When the
photoresist is developed, depending on what type of
photoresist was used, either the parts that were exposed to
light or the parts that were not exposed to light will
remain. The exposed gate material, i.e. without photoresist
on top, is chemically etched away, leaving the desired gate
pattern. Finally, ashing removes the remaining photoresist.
transistors are too close, they can electrically interfere
with one another. With up to billions of transistors on a
single chip, they might be separated by only the space of
only one one-hundredth of a human hair. Despite this
proximity, there are a few ways to prevent transistors from
interfering with one another. Dummy gates, which lack source
and drain regions, can separate transistors. In addition,
field oxide can be used as an insulator to cover the portions
of the substrate that do not have active transistors, and
gates can be formed on top of the field oxide.
time of the '352 Patent, transistor feature sizes had
decreased and were approaching 45 nm
'352 Patent 1:27-30. Because those feature sizes are
smaller than the wavelength of light, unintended interactions
can occur between neighboring features during lithography.
See Id. at 1:24-27. Specifically, unwanted shapes
may be created (constructive interference) or desired shapes
may be removed (destructive interference). Id.
1:35-41. The patented technology aims to create a solution
“for managing lithographic gap issues as technology
continues to progress toward smaller semiconductor device
features sizes.” Id. at 1:49-51.
parties agree on the construction of the following two terms:
selected portions of the substrate within which
impurities have been introduced to form the source
or drain of a transistor
“a lithography process”
plain and ordinary meaning, i.e., a process by
which a pattern is imprinted on a resist or
semiconductor wafer using light using a mask
Claim Construction and Prehearing Statement [Dkt. No. 163] 2.
The parties dispute seven terms, and I construe them as
“linear gate electrode segment, linear conductor
segment(s), linear conductive segment(s), and (interconnect)
linear conductive structures”
a 3D conductive structure having a rectangular shape
of a given width defined in a plane parallel to a top
surface of the substrate and defined to have a length
that extends in one direction
having a consistent vertical cross-section shape and
extending in a single direction over the substrate
extending in a single direction over the substrate
â352: 1, 17; â966: 2, 31, 33; â012: 2, 8, 11, 13, 28
parties first dispute the term “linear, ” which
is found in the '352, '966, and '012 Patents.
Tela argues that “linear” is to be defined and
understood from the top-down view, while Intel counters that
it should be understood in terms of a cross-section view.
Because the claims themselves do not support the limitation
Intel seeks to place on the term, nor does the specification
clearly do so, I agree with Tela's position on the term
The plain and ordinary meaning of the claim language
by analyzing the language of the claims themselves. Claim 2
of the '966 Patent reads in part, “wherein the gate
electrode level region includes a plurality of linear
conductive segments each formed to have a respective length
and a respective width as measured parallel to the substrate
region . . . .” '966 Patent 27:45-48. Claim 2 of
the '012 Patent reads, “wherein the gate electrode
level region includes a plurality of linear conductive
segments each formed to have a respective length and a
respective width as measured parallel to the substrate region
. . . .” '012 Patent 33:3-6.
language shows-and the parties agree-that
“linear” at the very least means free of bends on
the x-y axis. Op'g 10; Resp. 11. Indeed, that is the
plain and ordinary meaning of the term: a straight line.
According to Tela, this understanding is enough to construe
the term because “linear” is properly understood
according to the x-y axis, from the top-down view. Because
the patents are directed to layout files, and features in a
layout file are defined from a top view, this term too should
be understood from the top view. See Liu Decl. Ex.
7, Declaration of Daniel Foty (“Foty Decl.”)
[Dkt. No. 166-8] ¶ 83 (asserting that the patentee used
“linear” from the top view).
difficulty with construing this term arises from the fact
that-despite the patents' focus on the x- and y-axes
rather than the z-axis-“linear features” are
three-dimensional. The specifications of the Asserted Patents
do not describe or represent linear features only from the
top view, although Tela rightly points out that most figures
show that perspective. See Reply 3. But the patents
do include and describe some three-dimensional figures.
Because the claim language does not expressly address the
z-axis of linear-shaped features, it is necessary to review
the intrinsic evidence to determine whether it clearly
communications anything about the z-axis. My review of the
intrinsic evidence is guided by this admonition from the
[E]ven where a particular structure makes it
‘particularly difficult' to obtain certain benefits
of the claimed invention, this does not rise to the level of
disavowal of the structure. It is likewise not enough that
the only embodiments, or all of the embodiments, contain a
particular limitation. We do not read limitations from the
specification into claims; we do not redefine words. Only the
patentee can do that. To constitute disclaimer, there must be
a clear and unmistakable disclaimer.
Thorner v. Sony Computer Entm't Am. LLC, 669
F.3d 1362, 1366-67 (Fed. Cir. 2012) (internal citation
The intrinsic evidence
specification serves as “the single best guide to the
meaning of a disputed term.” See Phillips, 415
F.3d at 1315. The specification of the patents at issue
primarily discusses linear features by reference to the x and
y directions. For example, the '352 Patent reads,
“It should be appreciated that the linear-shaped
feature may be oriented to have its length 305 extend in
either the first reference direction (x), the second
reference direction (y), or in diagonal direction defined
relative to the first and second reference directions (x) and
(y). . . . Also, it should be understood that the